1. Field of the Invention
This invention relates to the processing of a semiconductor wafer to form an integrated circuit structure thereon. More particularly, this invention relates to an improved process for forming a layer of titanium silicide on a semiconductor wafer using a single annealing step.
2. Description of the Related Art
In the conventional formation of a titanium silicide layer, as a part of an integrated circuit structure on a semiconductor wafer such as a silicon wafer, those surfaces of the wafer on which the titanium silicide layer is to be formed are first cleaned to remove any materials which might interfere with reaction between the subsequently deposited titanium layer and the exposed silicon portions of the wafer. The surfaces are conventionally cleaned in a vacuum chamber using an inert gas such as argon with an rf plasma. This is sometimes preceded by an oxide wet etch.
Following these cleaning steps, a layer of titanium metal is conventionally deposited over the cleaned wafer structure, for example, using a vacuum sputtering deposition (PVD) process, usually to a thickness ranging from about 100 to about 1000 Angstroms.
The titanium coated wafer is then conventionally removed from the PVD chamber and transported through the ambient atmosphere to separate annealing apparatus where the structure is annealed in a nitrogen atmosphere and in the absence of oxygen (which would react with the titanium). Usually this annealing step comprises a rapid anneal where the structure is rapidly heated to the annealing temperature of from about 650.degree. to about 675.degree. C. in a few seconds and then maintained at this annealing temperature for from about 20 to about 60 seconds.
The nitrogen atmosphere used in this annealing step results in the simultaneous formation of a titanium nitride layer as the titanium reacts with the silicon to form titanium silicide. This titanium nitride acts as a blocking layer to prevent migration of silicon atoms to the surface, from the underlying silicon.
Following this anneal step, the wafer is conventionally removed from the annealing chamber and subjected to a wet etch to remove the titanium nitride blocking layer, as well as any remaining unreacted titanium. The etched wafer is then annealed again, however at a higher temperature of from about 800.degree. to about 900.degree. C., to convert the less stable C49 phase titanium silicide formed during the first annealing step to the more stable C54 phase.
The reason for annealing at a lower temperature during the first annealing step is to inhibit the formation of titanium oxide, (for example, by breakdown of the silicon oxide (SiO.sub.2) comprising insulated regions on the surface of the wafer and reaction of the resulting oxygen with titanium), as well as to permit formation of the desired blocking layer of titanium nitride over the surface.
The reason for conducting the etching step prior to the second, higher temperature, anneal is to ensure removal from the wafer of any unreacted titanium, particularly unreacted titanium remaining over insulated areas, which might otherwise result in reaction with oxygen from the silicon oxide during the higher temperature anneal. Such unreacted titanium can be the result of the presence of titanium oxides on the surface of the titanium layer which shield underlying portions of the titanium layer over the insulated regions of the wafer from reaction with the nitrogen gas present in the annealing chamber during the first annealing step.
It would, however, be desirable to provide a process for the formation of a titanium silicide layer on a semiconductor wafer wherein a single annealing step could be utilized, prior to the etching step, to avoid removing the wafer from the annealing chamber, wet etching the wafer, drying the wafer, and then reintroducing the etched wafer back to the annealing chamber for a second annealing step.